Corridor Tape‑Lattice Hybrid Computer

What’s new (v2): Explicit Turing Fabric comprised of a Photonic Delay Tape (PDT) and a Hardware Tape Accelerator (HTA on FPGA); dual‑cycle control (speculative photonic, commit electronic); ephemeral memory lanes; and a pin‑compatible carrier that keeps your tactile TP‑4/TD‑12 and panel geometry from v1.

Design Goals

Make the tape model a real device (not an emulator) with head moves and δ‑table transitions in hardware.
Keep Von Neumann SOM for OS, toolchains, and GPU while offloading stream/graph workloads to HTA.
Guarantee determinism with epoch commits at tape frame boundaries.
Use ephemeral buffers for one‑shot intermediates; no reuse by default.

High‑Level Path

[Userland Task] ↓ compile (graph→δ) [Transition Table (TTRAM)] + [Tape micro‑ISA] ↓ PCIe x4 [FPGA HTA] ──┬─ (digital ring tape BRAM) └─ [PDT] fiber delay loops (optional) ↓ results (epochs) [SOM CPU/GPU] ↔ FFM control plane ↔ Storage/Network

Computational Stack (Dual‑Cycle)

Plane A — Speculative / Wave Cycle

PDT: optical delay loops store pulses (bits/marks) for O(µs) lifetimes.
HTA: FPGA performs δ(q,s) → (q',s',dir) on BRAM ring or PDT sampled windows.
Ephemeral lanes: one‑time buffers auto‑invalidated post‑DMA.

Plane B — Commit / State Cycle

SOM CPU/GPU merges results, updates non‑ephemeral state and files.
FFM epoch commit flips staged shares/reservations in one barrier.
OS enforces human‑centric and eye‑safety policy.

Block Diagram

┌───────────────┐ PCIe ┌───────────────┐ LVDS/ADC ┌──────────┐ │ SOM (CPU/GPU) ├──────────► FPGA (HTA) ├──────────────► PDT │ │ LPDDR + FFM │◄──────────┤ (δ, BRAM) │◄──────────────┤ (loops) │ └───────┬───────┘ └───────────────┘ └────┬─────┘ │ NVMe / CXL LED PWM / │ │ PD TIA │ └────────────────────────────── human I/O ──────────────┘

Turing Fabric: PDT + HTA

Photonic Delay Tape (PDT)

Dual fiber loops (A/B) with couplers = two tapes or one duplex tape.
Write: LED driver → E/O injection window; Read: photodiode + TIA → ADC window.
Windowing synced by HTA timebase; sampling jitter budget < 1/10 symbol.
Optional only — BRAM ring is default tape for dev bring‑up.

Hardware Tape Accelerator (HTA) on FPGA

Tape BRAM Ring: 1–4 lanes, configurable alphabet (1/2/4/8‑bit symbol), head index pointer.
TTRAM: δ table RAM: (state, sym) → (state', sym', dir) with 16‑bit fast path and 24/32‑bit extended modes. Dir is explicit 2‑bit (00=L,01=R,10=N,11=RES/ERR).
µISA Front‑End: DEFINE_TRANS, MOVL/MOVR, WR0/WR1, STEP, RUN, RUN_EPOCHS n, HALT, SNAP, TRACE_SNAP.
CSR: head_pos, state, sym, epoch, status, EPOCH_LEN_2K, trace cfg/head/data, h_min, health/err IRQs.

Timing

Symbol rate (BRAM tape)	50–200 MHz (prototype)
Symbol rate (PDT)	100 ksym/s – 5 Msym/s (optic‑limited)
Epoch length	Power of two tape frames (e.g., 1024 steps) programmable via `EPOCH_LEN_2K`
Commit latency	< 10 µs after epoch boundary IRQ

Jitter budget (engineering constraint): Allowable sampling jitter is < 1/10 symbol period. Examples: at 1 Msym/s (1 µs period) → ≤ 100 ns; at 5 Msym/s (200 ns period) → ≤ 20 ns. Tie the ADC sampling clock phase noise/jitter spec to this budget when selecting parts.

⚡ Free-Form Memory (FFM) Architecture

x43 Nucleus Kernel with FFM Control Plane
Transactional control over HBM/DDR bandwidth shares, optical fabric reservations, and photonic admission governance. FFM implements epoch-based commits that integrate seamlessly with HTA tape boundaries.

🎚️ FFMShare (Staged)

Weights: HBM/DDR bandwidth shares (normalized 0..1)
Caps: Per-stack/channel bandwidth caps (Bps)
Fabric: Reserved Gbps for RT photonic jobs
QoS Flags: CUT_THROUGH_OPTX, RT_LOW_LATENCY
Epoch ID: Transaction identifier for atomic commits

📈 Telemetry (Live)

Bandwidth: Per-stack HBM/DDR utilization (Bps)
Fabric: TX/RX throughput (Gbps)
H-ratio: Photonic health (0..1)
Calibration: Duty cycle fraction
Queue Depth: OPTX tile job queue
Active Epoch: Currently running configuration

⚙️ Kernel API

k_ffm_set(FFMShare* share) → stage into shadow regs k_ffm_commit(uint64_t epoch) → atomic swap at safe barrier k_ffm_query(FFMTelem* telem) → one-shot telemetry snapshot /* Epoch commit integrates with HTA tape boundaries */

🔬 Ephemeral Memory

Optional FFM_EPHEMERAL buffer class
Software-enforced use-once semantics
Reads invalidate content post-DMA
Integrates with HTA SNAP instruction

📐 Form Factor Designs

Three form factors sharing the same TLH architecture: desktop (210×150×110mm), laptop (13.3″ class), and phone (6.1″ class) with tactile docking and consistent tape/FFM control.

Hardware Dimensions

Form Factor	Dimensions (W×D×H mm)	Weight	Display	Battery
Desktop	210×150×110	~1.8 kg	External (via TD-12)	AC powered
Laptop	305×215×15	~1.3 kg	13.3″ (1920×1080)	~55 Wh (3S)
Phone	150×72×8.5	~175 g	6.1″ OLED	~12 Wh

🖥️ Desktop Unit (210×150×110mm)

A. Outer shell
B. Base tray with PDT fiber bay
C. Optics board (LED/TIA/PD)
D. Baffle wall (fiber bay isolation)
E. 60mm fans ×2 (rear)
F. Tactile dock (TP-4/TD-12)
G. Main PCB (FPGA/HTA, ADC/PWM)
H. Power board (OR + 5V/3.3V/1.8V)
J. SOM (CPU+GPU+LPDDR)
K. M.2 (NVMe/FFM)

💻 Laptop (13.3″, 305×215×15mm)

Lid: Top-bezel optics (3 slots 2×22mm each, 6mm spacing)
M1: Mainboard (SOM + FPGA/HTA)
M2: M.2 (NVMe/FFM)
M3: Power/PD board
M4: Battery (~55 Wh 3S)
Thermals: Vapor chamber/heat-pipes
Ports: Left (2× USB-C, TP-4), Right (1× USB-C, microSD)

📱 Phone (6.1″, 150×72×8.5mm)

Top-edge optics: 3 micro-slots (1×12mm each)
Mainboard: SoC + LPDDR SOM-on-board
Battery: ~12 Wh
Thermal: Graphite/vapor spreader
Tactile pad (rear): 10-pin ~12×12mm (2×5 pads @ 3.5mm pitch)
Ports: USB-C bottom, rear accessory pad

Tactile Port Geometry

Interface	Desktop (rear)	Laptop	Phone
Optics windows	Front: 3 slots 4×70mm	Lid: 3 slots 2×22mm, 6mm spacing	Top edge: 3 micro-slots 1×12mm
TP-4 power	4 pads 5×8mm @ 8mm pitch	Left side, same geometry	Rear pad ~12×12mm; scaled 2.5×3.5mm pads
TD-12 data	3×4 pads 3.2×4.5mm	Left side dock	Rear accessory region
USB-C	2× rear	2× left + 1× right	1× bottom
PDT Bay	Ø95–120mm clear zone	Optional mini-loop	N/A (BRAM only)

Motherboard & Power (Pilot v2)

Top‑Level

┌──────────────────────────────────────────────────────────────┐ │ SOM (CPU+GPU+LPDDR) ── PCIe x4 ── FPGA (HTA + I/O) │ │ NVMe/CXL │ I2C/UART │ PWM/ADC │ TP‑4 / TD‑12 │ │ │ │ │ │ │ Power OR (USB‑PD + 12V + TP‑4) → 5V/3V3/1V8 rails │ └──────────────────────────────────────────────────────────────┘

Rails

OR: USB‑PD 20V + 12V barrel + TP‑4 (ideal diodes + precharge).
5V@8A → 3V3@5A → 1V8@1A. TVS on all externals.
Analog island for PD/TIA with RC + ground guard.

Keep‑outs (mech)

Retain v1 front/rear/right panel hole map; add PDT standoffs.
Fiber loop bay (Ø95–120 mm clear) with black baffles.

Photonic I/O & Safety

Emitter / Receiver

LEDs: 660 nm (primary), 470 nm (attenuated), or IR demo if preferred.
Drivers: constant‑current with PWM gating from FPGA.
PD: BPW34 class for demo; upgradeable to Si PIN (Hamamatsu).

Safety & Ops

Eye‑safety limiter in firmware; blue band attenuation user‑facing.
HELIOPASS calibration windows <= 2% duty; gate OPTX when H<h_min.

CSR Map & Tape Micro‑ISA

Control/Status Registers (PCIe BAR)

0x00	CTRL/STATUS: run, ERR_CLR, health_gate, err
0x02	EPOCH_LEN_2K: epoch length exponent (power‑of‑two frames)
0x04	STATE: q (current)
0x08	HEAD_POS: index
0x0A	EPOCH_LEN: length in steps (alternative to EPOCH_LEN_2K)
0x0C	EPOCH_ID: incremented each boundary
0x0E	H_MIN: health minimum threshold (Q1.15)
0x10	RUN_EPOCHS: bounded run counter
0x12	STEP_BUDGET: max steps before auto‑idle
0x20..	TTRAM Port: program δ entries
0x30	TRACE_CFG: sample every N steps (0=off)
0x32	TRACE_WPTR/RPTR: ring pointers
0x34..	TRACE_DATA: {epoch, head_pos} windows (state/sym adjacent)

Error semantics: err=1 on jitter_over_budget, adc_saturation, illegal δ entry (dir=11), tape underflow, or photonic health below H_MIN. A distinct IRQ (health gate) fires when H<H_MIN; it is not a HALT.

Micro‑ISA (host‑side)

DEFINE_TRANS q, sym -> q', sym', dir WR0 | WR1 ; write symbol MOVL n | MOVR n ; move head by n STEP k ; execute k transitions RUN ; run until HALT or epoch IRQ RUN_EPOCHS n ; run bounded number of epochs HALT SNAP dst,len ; copy tape window to host buffer (ephemeral) TRACE_SNAP dst,max ; copy trace ring (respects ephemeral) COMMIT_EPOCH ; flip staged FFM/HTA settings at boundary

See tape_micro_isa.md and tape_controller_stub.v.

δ‑Table Entry Widths

Fast path uses 16‑bit entries for binary demos. Extended modes use 24/32‑bit entries with explicit 2‑bit direction and configurable SYM_WIDTH (1/2/4/8). This provides headroom for quaternary symbols, byte‑wise streams, or cellular automata without hacks.

16‑bit: [ q'(8) | sym'(1) | dir(2) | res(5) ] 24/32‑bit: [ q'(8/16) | sym'(SYM_WIDTH) | dir(2) | res ]

Lane Semantics

1–4 lanes resident in BRAM. By default, transitions are independent per lane.
Optional coupling is supported via LANE_MASK and peek semantics (δ can read i±1 symbols for de‑risking multi‑tape algorithms).

Panels & Port Geometry

This build keeps your v1 hole table and adds PDT standoff points and a fiber bay. Use the CSV below in your CAD. Current sheet: rev 2, 2025‑10‑11. Optics windows (lid and top edge) allow ±0.2 mm tolerance on slot width and ±0.3 mm on spacing; maintain black baffles to reduce stray light.

port_placement.csv (PDT standoffs + fiber bay + v1 panels)
Reuse TD‑12 (data) and TP‑4 (power) pads from v1; same dimensions.

Bring‑Up & Test Plan (BoT)

FPGA bring‑up: loopback BRAM tape, blink head index on GPIO.
δ table smoke: 2‑state, 1‑symbol machine that toggles a LED.
Epoch IRQ: assert at 1024 steps; host COMMIT_EPOCH observed.
PDT loop: inject 1010 pattern, read with ADC window, compare BER.
Ephemeral DMA: SNAP into ephemeral buffer; verify auto‑invalidate.
Safety: enforce blue attenuation; HELIOPASS gating under H<h_min.

Downloads

tape_micro_isa.md tape_controller_stub.v port_placement.csv

Corridor — Tape‑Lattice Hybrid (TLH) Schematics